Optical Metrology of Semiconductor Wafers in Lithography

• Arie den Boef (ASML & ARCNL)

Room: H331 Abstract: The minimum feature size or Critical Dimension (CD) in semiconductor device manufacturing is steadily decreasing. In the production of these devices, optical lithography is an essential step. Today devices with a 22 nm features size are made by EUV lithography or double-patterning techniques using DUV hyper-NA lithography tools. Printing these small patterns in resist raises significant challenges for the metrology systems that are being used in lithography. For example, using a high NA and short wavelength yields a small depth-of-focus (DOF) which requires a level sensor that can measure wafer height variations with nm accuracy. Moreover, these small patterns must be printed with nm placement accuracy relative to underlying product patterns that are already present. This requires sub-nm accurate measurements of the position of the wafer before it is being exposed which is achieved with an optical alignment sensor. After the resist has been exposed and developed, the resulting resist pattern needs to be inspected for CD variations and pattern placement errors (Overlay) before it is being processed. This inspection step is often done with optical scatterometry. This presentation will give a concise explanation of the 3 above-mentioned optical measurement systems: a level sensor, an alignment sensor and a scatterometer. It will be shown how these sensors solve the common challenge of realizing sub-nm precision on a large variety of product stacks in the presence of process variations.